# Sirune (sirune.tech)

Converts English specs into SystemVerilog assertions and constraints inside VS Code, and suggests root causes from simulation logs.

- Atlas card: https://inite.ai/en/atlas/sirune.tech
- Site: https://sirune.tech
- For: Verification engineers writing and debugging UVM testbenches inside their code editor
- Categories: dev
- Use 0/100 · alive 100/100

## Used for

- generate SystemVerilog assertions and constraints from plain-language test plans
- find likely root causes in simulation logs without manual grep
- debug failing simulations using RTL, testbench and log context

## Price

Not read yet.

## For developers

- MCP server: tech.sirune/manthan (namespace; auth on 2026-10-21)
- Read 2026-10-21

## MCP server, measured daily

Server: https://api.sirune.tech/mcp, checked every day since 2026-10-21 (13 checks).

- Answered: 100% of daily checks
- Median first answer: 778 ms
- Sign-in: OAuth (the client signs the user in)
- Method: https://inite.ai/en/atlas/mcp/report

## Your data

- Certifications stated: none
- Read 2026-10-21

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Source: INITE Atlas, https://inite.ai/en/atlas/sirune.tech. JSON: https://inite.ai/api/atlas/sirune.tech. MCP: https://inite.ai/api/mcp (atlas_lookup).